Memory architectures that utilize on-chip ECC often have limitations. For example, flash memory solutions employing large page ECC (e.g. 256 bit) may have re-write limitations. Flash memory solutions that use pseudo-single-bit per cell (PSBC) may have reliability limitations. PSBC is capable of correcting small shifts in the programmed state of any cell, but is not capable of correcting large shifts.
Phase change memory (PCM) utilizing ECC may be limited by the endurance of the parity cells.